The present invention relates to a divider circuit suitable for setting vertical addresses of color data in a system such as a character broadcast system or a caption system.
In a conventional character broadcast or caption system, a display screen is constituted by a dot matrix (248 horizontal pixels.times.204 vertical pixels). Coloring is, for example, performed in units of sub-blocks each having 8 horizontal pixels and 12 vertical pixels. Therefore, 8-bit X (horizontal) addresses 0 to 247 and 8-bit Y (vertical) addresses 0 to 203 are assigned to the display screen. When coloring is actually performed, quasi columns 0 to 30 along the horizontal direction and quasi rows 0 to 16 along the vertical direction are assigned to the sub-blocks. Each quasi column corresponds to eight horizontal pixels, and each quasi row corresponds to 12 vertical pixels. A dot pattern is read out from an image memory in units of eight horizontal pixels. Therefore, the dot pattern is designated in units of quasi columns 0 to 30 and Y addresses 0 to 203. Coloring is performed in units of sub-blocks, as described above, so that color data can be read out in units of quasi columns 0 to 30 along the horizontal direction but must be read out in units of 12-bit quasi rows along the vertical direction. Therefore, in order to prepare a Y address of color data, a quasi row converter is required wherein vertical addresses 0 to 203 having the dot pattern data are divided into units of 12 pixels and are converted to quasi rows 0 to 16.
The conventional sub-block as the unit of coloring comprises eight horizontal pixels and 12 vertical pixels. However, a minimization of a sub-block unit provides good coloring of display. From this, the preferred sub-block unit is expected to be smaller than that of the conventional sub-block. In this case, the Y addresses along the vertical direction of the screen must be quasi row-converted. If the quasi rows are arranged in units of two lines, four lines, or eight lines, and hence in units of 2.sup.n (n=1, 2, 3, . . . ), seven , six or five most significant bits of the 8-bit Y address can be easily quasi row-converted. However, if the quasi row is employed in units of three lines, six lines, nine lines, . . . , and hence in units of 3.sup.n (n=1, 2, 3, . . . ), the Y addresses must be quasi row-converted in units of three lines. With a combination of quasi row conversion in units of three lines and of two lines, all possible quasi row conversions such as two-, three-, four-, six-, eight-, nine- and 12-line quasi row conversions can be performed. In this case, two-line quasi row conversion can be easily performed by shifting each bit of the Y address. Therefore, it is important to consider the circuit configuration of a quasi row converter for performing quasi row conversion in units of three lines.
Table 1 below shows 8-bit Y addresses and their updated addresses obtained by quasi row-converting the 8-bit addresses in units of three lines. A quasi row converter for performing quasi row conversion in units of three lines will be described with reference to Table 1.
TABLE 1 __________________________________________________________________________ Y address Quasi row-converted address Decimal Decimal notation a.sub.7 a.sub.6 a.sub.5 a.sub.4 a.sub.3 a.sub.2 a.sub.1 a.sub.0 notation b.sub.6 b.sub.5 b.sub.4 b.sub.3 b.sub.2 b.sub.1 b.sub.0 __________________________________________________________________________ 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 3 0 0 0 0 0 0 1 1 4 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 5 0 0 0 0 0 1 0 1 6 0 0 0 0 0 1 1 0 7 0 0 0 0 0 1 1 1 2 0 0 0 0 0 1 0 8 0 0 0 0 1 0 0 0 9 0 0 0 0 1 0 0 1 10 0 0 0 0 1 0 1 0 3 0 0 0 0 0 1 1 11 0 0 0 0 1 0 1 1 12 0 0 0 0 1 1 0 0 13 0 0 0 0 1 1 0 1 4 0 0 0 0 1 0 0 14 0 0 0 0 1 1 1 0 15 0 0 0 0 1 1 1 1 16 0 0 0 1 0 0 0 0 5 0 0 0 0 1 0 1 17 0 0 0 1 0 0 0 1 18 0 0 0 1 0 0 1 0 19 0 0 0 1 0 0 1 1 6 0 0 0 0 1 1 0 20 0 0 0 1 0 1 0 0 21 0 0 0 1 0 1 0 1 22 0 0 0 1 0 1 1 0 7 0 0 0 0 1 1 1 23 0 0 0 1 0 1 1 1 24 0 0 0 1 1 0 0 0 25 0 0 0 1 1 0 0 1 8 0 0 0 1 0 0 0 26 0 0 0 1 1 0 1 0 27 0 0 0 1 1 0 1 1 28 0 0 0 1 1 1 0 0 9 0 0 0 1 0 0 1 29 0 0 0 1 1 1 0 1 246 1 1 1 1 0 1 1 0 247 1 1 1 1 0 1 1 1 82 1 0 1 0 0 1 0 248 1 1 1 1 1 0 0 0 249 1 1 1 1 1 0 0 1 250 1 1 1 1 1 0 1 0 83 1 0 1 0 0 1 1 251 1 1 1 1 1 0 1 1 252 1 1 1 1 1 1 0 0 253 1 1 1 1 1 1 0 1 84 1 0 1 0 1 0 0 254 1 1 1 1 1 1 1 0 255 1 1 1 1 1 1 1 1 85 1 0 1 0 1 0 1 __________________________________________________________________________ P A three-line quasi row conversion can be exemplified using a read-only memory (ROM). An 8-bit Y address is regarded as a ROM address, and a quasi row-converted address of data is written in the ROM. More particularly, 7-bit addresses b.sub.6 b.sub.5 b.sub.4 b.sub.3 b.sub.2 b.sub.1 b.sub.0 obtained by quasi row conversion as data corresponding to addresses 0 to 255, each of which consists of 8-bit data a.sub.7 a.sub.6 a.sub.5 a.sub.4 a.sub.3 a.sub.2 a.sub.1 a.sub.0, are written in the ROM.
However, in order to form an integrated system including a quasi row converter, the quasi row converter having the ROM requires 1792 (=256.times.7) memory cells and a corresponding Y address decoder. Therefore, the above quasi row converter requires a large amount of hardware and is not suitable for an IC.
Another exemplification of quasi row conversion in units of three lines is a logic converter for performing the conversion shown in Table 1. Bits b.sub.0 to b.sub.7 of the quasi row-converted address can be designated by logic expressions using bits a.sub.0 to a.sub.7 of the Y address as follows: ##EQU2## PG,7
The logic expressions for bits b.sub.1 and b.sub.0 are omitted since they are too long. As will be apparent from the above description, when the quasi row converter for performing quasi row conversion in units of three lines comprises a logic circuit, the amount of hardware is greatly increased as in the case of the quasi row converter using ROM. These conventional quasi row converters are not suitable for an IC.